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Anurag Goyal

Anurag Goyal

Digital ASIC/FPGA Design | Sr. SOC Design Engineer at Xilinx | 6+ years experience

San Jose, California

Experienced in Digital ASIC/FPGA Design, currently working as Sr. SOC Debug and Diagnostic Engineer at Xilinx. Skilled in RTL Design, Computer Architecture and DFT. Strong engineering professional with a Master’s Degree focused in Electrical and Electronics Engineering from the University of Southern California.


  • Hardware Engineering Intern (Signal Laboratories, Inc.)
  • Research Intern (Technical University of Ilmenau)
  • Sr. Design Engineer (Xilinx)
  • Research Intern (Solid State Physics Laboratory, Defense Research & Development Organisation)
  • Assistant Manager (Reliance Jio Infocomm Ltd.)
  • Hardware Engineer (Signal Laboratories, Inc.)


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