Specification Engineer at Nokia @ Vantaa, Uusimaa
ASIC Design Engineer at Intel Corporation
Santa Clara, California
• ASIC/ SOC RTL frontend Functional Design and Micro-architecture and Verification Engineer
• Writing Hardware Design Document (HDD) for the architecture.
• SoC integration of multi-million gate design
• Soft IP micro-architecture and RTL design in System Verilog for 32nm, 22nm, 16ff, 14nm process.
• Experience in PCIe Gen3 (Digital), Network-on-Chip (NOC), OCP, AXI, AHB, TAP etc. protocols.
• FPGA Prototyping and Lab debug experience using Chip-scope and logic-analyzer.
• Experience high-speed (max of 1 GHz) multi-clock controller design from scratch and IP integration.
• Knowledge in Synthesis using Synopsys Design Compiler, CDC using 0-in, Mentor Graphics DFT Advisor/and Fast Scan and Conformal for formal verification (LEC), FPGA synthesis using Synplify.
• Knowledge in X86 System architecture, Cache architecture, Snoopy Protocol, System Instructions etc.
• Experience in leading a team on a project from Micro-Arch to RTL for a Soft IP development.
• Experience in System Verilog based OVM, UVM, Constraint Random Verification and assertions.
• Knowledge in low-power design, UPF and STA.