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Ching-Chi Chang

Ching-Chi Chang

Design Verification Engineer at Intel Corporation Programmable Solutions Group

San Jose, California

- Strong background in memory interface verification in IO subsystem level
- Extensive experience in ASIC verification methodology using System Verilog, UVM and VMM
- Experienced in memory controller block level verification
- Experienced in custom design and verification of external memory interface PHY circuitry

Specialties: - System Verilog constrained-random/coverage-driven verification
- Extensive knowledge in different kinds of SDRAM protocols and controller operations
- DDRx (JESD79 including DDR4 and DDR3)
- LPDDRx (JESD209 including LPDDR3)
- HBM
- RLDRAM3

- Knowledge of high speed AXI protocol
- Knowledge of Avalon MM/Avalon ST protocol
- RTL coding in Verilog
- Custom design and verification


Experience:

  • Design Verification Manager (Intel Corporation)
  • Design Verification Engineer (Intel Corporation)
  • Design Verification Engineer (Altera)
  • Design Engineer (Altera)

Skills:

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