Improver

Hayk Chukhajyan

Manager II, R&D, Synopsys

Armenia

- SoC-level and core level DFT solution
- IEEE 1149.1, 1687, 1500, 1838 support
- ICL/PDL conversion to MASIS
- DFT solutions for memories, AMS, Interface IP
- Data formats for DUT description and DFT generation (MASIS interfacing)
- FE compilers for memories, AMS, Interface IP
- RTL MASIS-based compiler for e-fuses
- RTL design and verification
- Embeded systems
- HDL (Verilog, VHDL, SystemVerilog)
- Scripting
- SW tools for DFT automation
- RTL drivers for non-volatile data containers

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Experience:

• RTL Design Manager (Virage Logic)
• Hardware Design Engineer (Credence Systems)
• Manager II, ASIC Digital Design (Synopsys)
• RTL design engineer (Virage Logic)
• Memory DFT automation manager (Virage Logic)
• Manager II, R&D (Synopsys Inc)

Skills:

• SoC
• HDL modeling
• RTL Design
• DFT, including memory DFT
• ICL/PDL conversion to MASIS
• Testing
• DFT
• Hardware and software development
• Integrated Circuit Design
• Debugging
• RTL Coding
• EDA
• ASIC
• R&D management
• Hardware Architecture
• VHDL
• Memories
• IEEE 1149.1, 1687, 1500, 1838 support
• VLSI
• TCL
• Logical design
• Verilog
• SystemVerilog
• Functional Verification