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Pawandeep Sawhney

Pawandeep Sawhney

Design Verification Engineer at Microsoft

San Francisco Bay Area

Hardware design and verification engineer with over 5 years of experience of successfully developing and testing various verification testbench infrastructure and simulation models across various Intel IPs, transceiver (HSSI) subsystem as well as Integrated I/O (PCIe, IOSF) subsystem. Well versed with various verification languages (Verilog, SystemVerilog) and methodologies like UVM, OVM.


Experience:

  • Design Verification Engineer (Microsoft)
  • SoC Design Verification Engineer, Server Group (Intel Corporation)
  • IP Design Verification Engineer (Intel Corporation)
  • Engineer (Bharat Heavy Electricals Limited)

Skills:

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