Full-stack Developer @ Tel Aviv
Sr. Staff Engineer at Juniper Networks
Sr. Staff Engineer Signal Integrity. ASIC on chip clock tree simulation & design. ASIC design chips supporting High Speed Serdes up to 56.25Gb/s PAM4 modulation. System design including WAN IO optics for Ethernet applications 100G QSFP28 LR, SR CWDM, PSM and 400G QSFP-DD FR, LR. System board design lead Line Cards, Switch Interface Board for Data Center applications. System bring up, SI validation measurements and Pilot build system level test supporting First Revenue Shipments.