Owner, CEO, CHRO! @ Telangana
Senior Design Engineer at Xilinx
Santa Clara, California
3.5 years of circuit design experience in advanced CMOS processes from 65nm to 28nm.
Experience with high speed multi-protocol Serdes and DDR3 IPs including TX, RX, PLL, DLL, CDR.
-Schematic capture, simulations in SPICE, post-layout analysis.
-Work with back-end and layout engineers to implement and verify the design
Tools and simulators: Cadence Virtuoso, Calibre-Layout, DRC, LVS, PEX, Modelsim , hspice, spectre, APS,AMS ,MATLAB
Programming and scripting Languages: Verilog-A, Verilog HDL, VHDL, Assembly Language, C, C++, PERL, HTML